Silicon piezoresistive stress sensors and their application in electronic packaging

Abstract

Structural reliability of integrated circuit (IC) chips in electronic packages continues to be a major concern due to ever-increasing die size, circuit densities, power dissipation, operating temperatures, and the use of a wide range of low-cost packaging materials. A powerful method for experimental eval- uation of silicon die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, a review is made of the state-of-the-art in the area of silicon piezore- sistive stress sensor test chips. Developments in sensor theory, calibration methods, and packaging applications are presented. In the absence of die failure, packaging-induced stresses result in changes in the parametric performance of circuitry on the die, and the theory discussed here can be used to predict such changes. Index Terms—Electronic packaging, piezoresistive, stress sensor, test chip.