articleTop 10% cited
Scaling theory for double-gate SOI MOSFET's
IEEE Transactions on Electron Devices · 1993 · Vol. 40(12) · pp. 2326–2329
Ken Suzuki✉(Fujitsu (Japan))Tetsu Tanaka(Fujitsu (Japan))Y. Tosaka(Fujitsu (Japan))Hiroshi Horie(Fujitsu (Japan))Y. Arimoto(Fujitsu (Japan))
Abstract
A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Advancements in Semiconductor Devices and Circuit DesignSemiconductor materials and devicesSilicon Carbide Semiconductor TechnologiesSubthreshold conductionSilicon on insulatorMOSFETScalingSubthreshold slopeIdeal (ethics)Gate oxideSiliconOptoelectronicsPhysics
Citations
555
FWCI
6.44
field-weighted impact
References
17
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References
Scaling the Si MOSFET: from bulk to SOI to bulk
IEEE Transactions on Electron Devices · 1992 · 888 citations
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