Comprehensive modeling of hot carrier degradation in full VG-VD space across diverse experimental conditions and architectures

Abstract

Hot Carrier Degradation (HCD) remains a critical reliability concern in advanced CMOS devices, particularly with aggressive scaling in technology nodes and the adoption of novel architectures like FinFETs and nanosheet transistors. This study aims to develop a comprehensive physics-based HCD model validated across the full VG-VD (gate voltage-drain voltage) operational space under varying stress conditions, device architectures, and temperatures. A range of CMOS devices, including planar MOSFETs, FinFETs, and nanosheet transistors from 7nm, 10nm, and 14nm technology nodes, were subjected to prolonged electrical stress. Measurements of threshold voltage shifts (ΔVth), drain current degradation (ΔID), and subthreshold swing variations (SS) were conducted using precision parameter analyzers, charge-pumping techniques, and deep-level transient spectroscopy (DLTS). Temperature effects (25°C, 75°C, 125°C) and stress durations (10s to 10,000s) were analyzed, and numerical simulations using TCAD tools validated the experimental results. The study found that nanosheet transistors exhibited the lowest degradation metrics (ΔVth = 60mV, ΔID = 10%, SS = 8mV/decade) compared to planar MOSFETs (ΔVth = 120mV, ΔID = 25%, SS = 25mV/decade) and FinFETs (ΔVth = 90mV, ΔID = 15%, SS = 15mV/decade). Temperature was found to exacerbate degradation effects, with defect density peaking at higher stress temperatures. Statistical validation via ANOVA confirmed significant differences among architectures (p < 0.001), and regression models revealed strong correlations between operational parameters and HCD behavior (R² = 0.92). The proposed HCD model demonstrated predictive accuracy with error margins below ±5%. Practical recommendations include prioritizing nanosheet transistor adoption, optimizing operational voltages, improving gate dielectric quality, and integrating thermal management strategies. These findings offer a robust framework for enhancing device reliability and advancing semiconductor technology.