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Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule

IEEE Transactions on Electron Devices · 2010 · Vol. 57(7) · pp. 1527–1538
Eishi IbeHitoshi TaniguchiY. YahagiKenichi ShimboTadanobu Toba

Abstract

Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have less than 20% variations from experimental soft-error data on 180-130 nm SRAMs in a wide variety of neutron fields like field tests at low and high altitudes and accelerator tests in LANSCE, TSL, and CYRIC. The following results are obtained: 1) Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller size, soft-error rate is dominated more significantly by low-energy neutrons (<; 10 MeV); and 3) The area affected by one nuclear reaction spreads over 1 M bits and bit multiplicity of multi-cell upset become as high as 100 bits and more.

Radiation Effects in ElectronicsVLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisSoft errorUpsetStatic random-access memoryNeutronMonte Carlo methodScalingPhysicsMaterials scienceComputational physicsNuclear physics

Funding

  • California Institute of Technology
  • Division of Electrical, Communications and Cyber Systems
Citations
488
FWCI
18.49
field-weighted impact
References
44
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99%
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References
Upset hardened memory design for submicron CMOS technology
IEEE Transactions on Nuclear Science · 1996 · 1,131 citations
Charge Collection and Charge Sharing in a 130 nm CMOS Technology
IEEE Transactions on Nuclear Science · 2006 · 394 citations
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