article

Upset hardened memory design for submicron CMOS technology

IEEE Transactions on Nuclear Science · 1996 · Vol. 43(6) · pp. 2874–2878

T. Calin✉(Techniques of Informatics and Microelectronics for Integrated Systems Architecture)M. Nicolaidis(Techniques of Informatics and Microelectronics for Integrated Systems Architecture)Raoul Velazco(Techniques of Informatics and Microelectronics for Integrated Systems Architecture)

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Abstract

A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.

Radiation Effects in Electronics VLSI and Analog Circuit Testing Integrated Circuits and Semiconductor Failure AnalysisCMOSSingle event upsetUpsetElectronic engineeringRadiation hardeningComputer scienceEmbedded systemStatic random-access memoryMaterials scienceElectrical engineering

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