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Charge Collection and Charge Sharing in a 130 nm CMOS Technology

IEEE Transactions on Nuclear Science · 2006 · Vol. 53(6) · pp. 3253–3258
Oluwole A. AmusanArthur F. WitulskiL. W. MassengillB. L. BhuvaPatrick R. FlemingMichael L. AllesAndrew L. SternbergJeffrey D. BlackRonald D. Schrimpf

Abstract

Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hit node and adjacent nodes are quantified. Results show that for a twin-well CMOS process, PMOS charge sharing can be effectively mitigated with the use of contacted guard-ring, whereas a combination of contacted guard-ring, nodal separation, and interdigitation is required to mitigate the NMOS charge sharing effect for the technology studied

Radiation Effects in ElectronicsVLSI and Analog Circuit TestingPhysical Unclonable Functions (PUFs) and Hardware SecurityCharge sharingNMOS logicPMOS logicCharge (physics)CMOSOptoelectronicsMaterials scienceTransistorElectrical engineeringComputer science

Funding

  • Vanderbilt University
Citations
394
FWCI
20.26
field-weighted impact
References
12
Percentile
100%
vs. same field & year
Citations per year
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References
Basic mechanisms and modeling of single-event upset in digital microelectronics
IEEE Transactions on Nuclear Science · 2003 · 1,105 citations
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