articleTop 1% cited
The TimberWolf placement and routing package
IEEE Journal of Solid-State Circuits · 1985 · Vol. 20(2) · pp. 510–522
Carl Sechen✉(University of California, Berkeley)Alberto Sangiovanni‐Vincentelli(University of California, Berkeley)
Abstract
TimberWolf is an integrated set of placement and routing optimization programs. The general combinatorial optimization technique known as simulated annealing is used by each program. Programs for standard cell, macro/custom cell, and gate-array placement, as well as standard cell global routing, have been developed. Experimental results on industrial circuits show that area savings over existing layout programs ranging from 15 to 62% are possible.
VLSI and FPGA Design TechniquesVLSI and Analog Circuit Testing3D IC and TSV technologiesPlacementStandard cellSimulated annealingMacroRouting (electronic design automation)Computer scienceSet (abstract data type)Network routingPhysical designParallel computing
Funding
- Intel Corporation
Citations
529
FWCI
28.50
field-weighted impact
References
8
Percentile
100%
vs. same field & year
Citations per year
References
On the shortest spanning subtree of a graph and the traveling salesman problem
Proceedings of the American Mathematical Society · 1956 · 5,025 citations
Optimization by Simulated Annealing
Science · 1983 · 44,165 citations
On the Shortest Spanning Subtree of a Graph and the Traveling Salesman Problem
Proceedings of the American Mathematical Society · 1956 · 1,123 citations
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The TimberWolf placement and routing package
IEEE Journal of Solid-State Circuits · 1985 · 529 citations
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