Enhancing 65nm CMOS microcircuit efficiency using neural network-based dynamic voltage scaling and multi-threshold techniques: A cadence virtuoso simulation and fabrication approach

Abstract

The increasing demand for energy-efficient CMOS microcircuits has led to significant research into techniques for reducing power consumption while maintaining performance. This paper explores the integration of Neural Network (NN) algorithms with Dynamic Voltage Scaling (DVS) and Multi-Threshold CMOS (MTCMOS) techniques to optimize power efficiency in 65nm CMOS microcircuits. Using Cadence Virtuoso for simulation and fabrication, we demonstrate how NN models can predict optimal voltage and threshold parameters under varying workloads, resulting in substantial power savings without compromising circuit performance. Our approach combines predictive analytics, hardware optimization, and fabrication feasibility, offering a robust framework for designing next-generation energy-efficient microcircuits.