AI-enhanced edge devices, real-time signal processing, Internet of Things (IoT), latency reduction, bandwidth efficiency

Abstract

The rapid expansion of wireless communication networks, particularly with the advent of 5G and the anticipated deployment of 6G, has intensified the demand for energy-efficient hardware solutions. Very-Large-Scale Integration (VLSI) circuits lie at the core of wireless transceivers, enabling tasks such as modulation, channel coding, and multi-antenna signal detection. However, scaling to nanometer technology nodes has heightened leakage currents, power density, and variability, thereby making low-power design a pressing challenge. This study investigates a holistic approach that integrates circuit-, architecture-, and system-level methodologies to address these constraints. Using 28 nm and 16 nm CMOS test cases, the research applied near-threshold voltage operation, fine-grained power gating, multi-Vt strategies, and workload-aware dynamic voltage and frequency scaling. Furthermore, architectural innovations such as reconfigurable LDPC and Polar decoders, pipeline-friendly MIMO detectors, and SRAM-based in-memory computing macros were implemented to evaluate their effectiveness in energy reduction. Experimental validation demonstrated average energy savings of 33-36% per bit across representative wireless baseband blocks, accompanied by throughput gains of 4-6% without loss of error-correction accuracy. At the system level, adaptive DVFS improved energy efficiency by 27-39% across variable traffic loads. These outcomes confirm the hypothesis that a cross-layer design methodology can deliver significant reductions in power consumption while sustaining performance requirements for future wireless systems. The study concludes that practical deployment of low-power VLSI design principles will be essential for enabling scalable, sustainable, and high-performance wireless communication infrastructures in the era of ubiquitous connectivity.