Enhancing logic circuit efficiency through power-performance-area optimization using clock-gating, multi-threshold CMOS, and FPGA-based validation

Abstract

The increasing demand for energy-efficient and high-performance logic circuits necessitates advanced optimization techniques that balance power, performance, and area (PPA) trade-offs. This study explores the effectiveness of clock-gating and multi-threshold CMOS (MTCMOS) techniques in minimizing power dissipation while maintaining performance integrity. The primary objective is to enhance logic circuit efficiency through PPA optimization, validated using FPGA-based prototyping. The methodology involves implementing clock-gating to reduce dynamic power and MTCMOS to mitigate leakage power, followed by hardware validation on the Xilinx Zynq-7000 SoC. Benchmark circuits from ISCAS'85 and ISCAS'89 were used to analyze the impact of optimizations on power consumption, delay, and area. The experimental results reveal a 25-40% reduction in power consumption (p = 0.0001) while maintaining minimal delay variations (±5%) (p = 0.3171) and insignificant area overhead (p = 0.0726). These findings confirm that clock-gating and MTCMOS provide a practical approach for low-power VLSI design without compromising circuit performance. The study also proposes adaptive clock-gating, dynamic voltage and frequency scaling (DVFS), and power-aware synthesis tools as future enhancements for further energy savings.