All-MOS charge redistribution analog-to-digital conversion techniques. I

Abstract

Describes a technique for performing A/D conversion compatibly with standard single-channel MOS technology. The use of a binary weighted capacitor array to perform a high-speed, successive approximation conversion is discussed. The technique provides an inherent sample/hold function and can accept both polarities of inputs with a single positive reference. The factors limiting the accuracy and conversion rate of the technique are considered analytically. Experimental results from a monolithic prototype are presented; a resolution of 10 bits was achieved with a conversion time of 23 /spl mu/s. The estimated die size for a completely monolithic version is 8000 mil/SUP 2/.