Impact of CMOS technology scaling on the atmospheric neutron soft error rate

Abstract

We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size L/sub G/. A different method, based on the MBGR model, predicts even faster decrease of SER per bit than linear. If the increasing number of bits is taken into account, then the SER per chip is not expected to increase faster than linearly with decreasing L/sub G/.