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A Two's Complement Parallel Array Multiplication Algorithm
IEEE Transactions on Computers · 1973 · Vol. C-22(12) · pp. 1045–1047
C.R. Baugh✉(Bell (Canada))B.A. Wooley
Abstract
An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive.
Interconnection Networks and SystemsCellular Automata and ApplicationsEngineering and Test SystemsMultiplication (music)Multiplication algorithmComplement (music)Multiplier (economics)ArithmeticBit (key)Computer scienceProduct (mathematics)MathematicsAlgorithm
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