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A precise four-quadrant multiplier with subnanosecond response

IEEE Journal of Solid-State Circuits · 1968 · Vol. 3(4) · pp. 365–373
B. Gilbert

Abstract

This paper describes a technique for the design of two-signal four-quadrant multipliers, linear on both inputs and useful from dc to an upper frequency very close to the f/SUB t/ of the transistors comprising the circuit. The precision of the product is shown to be limited primarily by the matching of the transistors, particularly with reference to emitter-junction areas. Expressions are derived for the nonlinearities due to various causes.

Analog and Mixed-Signal Circuit DesignAdvancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignQuadrant (abdomen)Multiplier (economics)TransistorCommon emitterElectronic engineeringFrequency multiplierAnalog multiplierElectrical engineeringBipolar junction transistorComputer science
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IEEE Journal of Solid-State Circuits · 2000 · 765 citations
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